/*
 * Copyright (c) 2014, Freescale Semiconductor, Inc.
 * All rights reserved.
 *
 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 */
/*
 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
 *
 * This file was generated automatically and any changes may be lost.
 */
#ifndef __HW_MTBDWT_REGISTERS_H__
#define __HW_MTBDWT_REGISTERS_H__

#include "MKL05Z4.h"
#include "fsl_bitband.h"

/*
 * MKL05Z4 MTBDWT
 *
 * MTB data watchpoint and trace
 *
 * Registers defined in this header file:
 * - HW_MTBDWT_CTRL - MTB DWT Control Register
 * - HW_MTBDWT_COMP0 - MTB_DWT Comparator Register
 * - HW_MTBDWT_MASK0 - MTB_DWT Comparator Mask Register
 * - HW_MTBDWT_FCT0 - MTB_DWT Comparator Function Register 0
 * - HW_MTBDWT_COMP1 - MTB_DWT Comparator Register
 * - HW_MTBDWT_MASK1 - MTB_DWT Comparator Mask Register
 * - HW_MTBDWT_FCT1 - MTB_DWT Comparator Function Register 1
 * - HW_MTBDWT_TBCTRL - MTB_DWT Trace Buffer Control Register
 * - HW_MTBDWT_DEVICECFG - Device Configuration Register
 * - HW_MTBDWT_DEVICETYPID - Device Type Identifier Register
 * - HW_MTBDWT_PERIPHID4 - Peripheral ID Register
 * - HW_MTBDWT_PERIPHID5 - Peripheral ID Register
 * - HW_MTBDWT_PERIPHID6 - Peripheral ID Register
 * - HW_MTBDWT_PERIPHID7 - Peripheral ID Register
 * - HW_MTBDWT_PERIPHID0 - Peripheral ID Register
 * - HW_MTBDWT_PERIPHID1 - Peripheral ID Register
 * - HW_MTBDWT_PERIPHID2 - Peripheral ID Register
 * - HW_MTBDWT_PERIPHID3 - Peripheral ID Register
 * - HW_MTBDWT_COMPIDn - Component ID Register
 *
 * - hw_mtbdwt_t - Struct containing all module registers.
 */

#define HW_MTBDWT_INSTANCE_COUNT (1U) /*!< Number of instances of the MTBDWT module. */

/*******************************************************************************
 * HW_MTBDWT_CTRL - MTB DWT Control Register
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_CTRL - MTB DWT Control Register (RO)
 *
 * Reset value: 0x2F000000U
 *
 * The MTBDWT_CTRL register provides read-only information on the watchpoint
 * configuration for the MTB_DWT.
 */
typedef union _hw_mtbdwt_ctrl
{
    uint32_t U;
    struct _hw_mtbdwt_ctrl_bitfields
    {
        uint32_t DWTCFGCTRL : 28;      /*!< [27:0] DWT configuration controls */
        uint32_t NUMCMP : 4;           /*!< [31:28] Number of comparators */
    } B;
} hw_mtbdwt_ctrl_t;

/*!
 * @name Constants and macros for entire MTBDWT_CTRL register
 */
/*@{*/
#define HW_MTBDWT_CTRL_ADDR(x)   ((x) + 0x0U)

#define HW_MTBDWT_CTRL(x)        (*(__I hw_mtbdwt_ctrl_t *) HW_MTBDWT_CTRL_ADDR(x))
#define HW_MTBDWT_CTRL_RD(x)     (HW_MTBDWT_CTRL(x).U)
/*@}*/

/*
 * Constants & macros for individual MTBDWT_CTRL bitfields
 */

/*!
 * @name Register MTBDWT_CTRL, field DWTCFGCTRL[27:0] (RO)
 *
 * This field is hardwired to 0xF00_0000, disabling all the remaining DWT
 * functionality. The specific fields and their state are: MTBDWT_CTRL[27] = NOTRCPKT =
 * 1, trace sample and exception trace is not supported MTBDWT_CTRL[26] =
 * NOEXTTRIG = 1, external match signals are not supported MTBDWT_CTRL[25] = NOCYCCNT =
 * 1, cycle counter is not supported MTBDWT_CTRL[24] = NOPRFCNT = 1, profiling
 * counters are not supported MTBDWT_CTRL[22] = CYCEBTENA = 0, no POSTCNT
 * underflow packets generated MTBDWT_CTRL[21] = FOLDEVTENA = 0, no folded instruction
 * counter overflow events MTBDWT_CTRL[20] = LSUEVTENA = 0, no LSU counter overflow
 * events MTBDWT_CTRL[19] = SLEEPEVTENA = 0, no sleep counter overflow events
 * MTBDWT_CTRL[18] = EXCEVTENA = 0, no exception overhead counter events
 * MTBDWT_CTRL[17] = CPIEVTENA = 0, no CPI counter overflow events MTBDWT_CTRL[16] =
 * EXCTRCENA = 0, generation of exception trace disabled MTBDWT_CTRL[12] = PCSAMPLENA =
 * 0, no periodic PC sample packets generated MTBDWT_CTRL[11:10] = SYNCTAP = 0,
 * no synchronization packets MTBDWT_CTRL[9] = CYCTAP = 0, cycle counter is not
 * supported MTBDWT_CTRL[8:5] = POSTINIT = 0, cycle counter is not supported
 * MTBDWT_CTRL[4:1] = POSTPRESET = 0, cycle counter is not supported MTBDWT_CTRL[0] =
 * CYCCNTENA = 0, cycle counter is not supported
 */
/*@{*/
#define BP_MTBDWT_CTRL_DWTCFGCTRL (0U)     /*!< Bit position for MTBDWT_CTRL_DWTCFGCTRL. */
#define BM_MTBDWT_CTRL_DWTCFGCTRL (0x0FFFFFFFU) /*!< Bit mask for MTBDWT_CTRL_DWTCFGCTRL. */
#define BS_MTBDWT_CTRL_DWTCFGCTRL (28U)    /*!< Bit field size in bits for MTBDWT_CTRL_DWTCFGCTRL. */

/*! @brief Read current value of the MTBDWT_CTRL_DWTCFGCTRL field. */
#define BR_MTBDWT_CTRL_DWTCFGCTRL(x) (HW_MTBDWT_CTRL(x).B.DWTCFGCTRL)
/*@}*/

/*!
 * @name Register MTBDWT_CTRL, field NUMCMP[31:28] (RO)
 *
 * The MTB_DWT implements two comparators.
 */
/*@{*/
#define BP_MTBDWT_CTRL_NUMCMP (28U)        /*!< Bit position for MTBDWT_CTRL_NUMCMP. */
#define BM_MTBDWT_CTRL_NUMCMP (0xF0000000U) /*!< Bit mask for MTBDWT_CTRL_NUMCMP. */
#define BS_MTBDWT_CTRL_NUMCMP (4U)         /*!< Bit field size in bits for MTBDWT_CTRL_NUMCMP. */

/*! @brief Read current value of the MTBDWT_CTRL_NUMCMP field. */
#define BR_MTBDWT_CTRL_NUMCMP(x) (HW_MTBDWT_CTRL(x).B.NUMCMP)
/*@}*/

/*******************************************************************************
 * HW_MTBDWT_COMP0 - MTB_DWT Comparator Register
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_COMP0 - MTB_DWT Comparator Register (RW)
 *
 * Reset value: 0x00000000U
 *
 * The MTBDWT_COMPn registers provide the reference value for comparator n.
 */
typedef union _hw_mtbdwt_comp0
{
    uint32_t U;
    struct _hw_mtbdwt_comp0_bitfields
    {
        uint32_t COMP : 32;            /*!< [31:0] Reference value for comparison */
    } B;
} hw_mtbdwt_comp0_t;

/*!
 * @name Constants and macros for entire MTBDWT_COMP0 register
 */
/*@{*/
#define HW_MTBDWT_COMP0_ADDR(x)  ((x) + 0x20U)

#define HW_MTBDWT_COMP0(x)       (*(__IO hw_mtbdwt_comp0_t *) HW_MTBDWT_COMP0_ADDR(x))
#define HW_MTBDWT_COMP0_RD(x)    (HW_MTBDWT_COMP0(x).U)
#define HW_MTBDWT_COMP0_WR(x, v) (HW_MTBDWT_COMP0(x).U = (v))
#define HW_MTBDWT_COMP0_SET(x, v) (HW_MTBDWT_COMP0_WR(x, HW_MTBDWT_COMP0_RD(x) |  (v)))
#define HW_MTBDWT_COMP0_CLR(x, v) (HW_MTBDWT_COMP0_WR(x, HW_MTBDWT_COMP0_RD(x) & ~(v)))
#define HW_MTBDWT_COMP0_TOG(x, v) (HW_MTBDWT_COMP0_WR(x, HW_MTBDWT_COMP0_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual MTBDWT_COMP0 bitfields
 */

/*!
 * @name Register MTBDWT_COMP0, field COMP[31:0] (RW)
 *
 * If MTBDWT_COMP0 is used for a data value comparator and the access size is
 * byte or halfword, the data value must be replicated across all appropriate byte
 * lanes of this register. For example, if the data is a byte-sized "x" value,
 * then COMP[31:24] = COMP[23:16] = COMP[15:8] = COMP[7:0] = "x". Likewise, if the
 * data is a halfword-size "y" value, then COMP[31:16] = COMP[15:0] = "y".
 */
/*@{*/
#define BP_MTBDWT_COMP0_COMP (0U)          /*!< Bit position for MTBDWT_COMP0_COMP. */
#define BM_MTBDWT_COMP0_COMP (0xFFFFFFFFU) /*!< Bit mask for MTBDWT_COMP0_COMP. */
#define BS_MTBDWT_COMP0_COMP (32U)         /*!< Bit field size in bits for MTBDWT_COMP0_COMP. */

/*! @brief Read current value of the MTBDWT_COMP0_COMP field. */
#define BR_MTBDWT_COMP0_COMP(x) (HW_MTBDWT_COMP0(x).U)

/*! @brief Format value for bitfield MTBDWT_COMP0_COMP. */
#define BF_MTBDWT_COMP0_COMP(v) ((uint32_t)((uint32_t)(v) << BP_MTBDWT_COMP0_COMP) & BM_MTBDWT_COMP0_COMP)

/*! @brief Set the COMP field to a new value. */
#define BW_MTBDWT_COMP0_COMP(x, v) (HW_MTBDWT_COMP0_WR(x, v))
/*@}*/

/*******************************************************************************
 * HW_MTBDWT_MASK0 - MTB_DWT Comparator Mask Register
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_MASK0 - MTB_DWT Comparator Mask Register (RW)
 *
 * Reset value: 0x00000000U
 *
 * The MTBDWT_MASKn registers define the size of the ignore mask applied to the
 * reference address for address range matching by comparator n. Note the format
 * of this mask field is different than the MTB_MASTER[MASK].
 */
typedef union _hw_mtbdwt_mask0
{
    uint32_t U;
    struct _hw_mtbdwt_mask0_bitfields
    {
        uint32_t MASK : 5;             /*!< [4:0] MASK */
        uint32_t RESERVED0 : 27;       /*!< [31:5]  */
    } B;
} hw_mtbdwt_mask0_t;

/*!
 * @name Constants and macros for entire MTBDWT_MASK0 register
 */
/*@{*/
#define HW_MTBDWT_MASK0_ADDR(x)  ((x) + 0x24U)

#define HW_MTBDWT_MASK0(x)       (*(__IO hw_mtbdwt_mask0_t *) HW_MTBDWT_MASK0_ADDR(x))
#define HW_MTBDWT_MASK0_RD(x)    (HW_MTBDWT_MASK0(x).U)
#define HW_MTBDWT_MASK0_WR(x, v) (HW_MTBDWT_MASK0(x).U = (v))
#define HW_MTBDWT_MASK0_SET(x, v) (HW_MTBDWT_MASK0_WR(x, HW_MTBDWT_MASK0_RD(x) |  (v)))
#define HW_MTBDWT_MASK0_CLR(x, v) (HW_MTBDWT_MASK0_WR(x, HW_MTBDWT_MASK0_RD(x) & ~(v)))
#define HW_MTBDWT_MASK0_TOG(x, v) (HW_MTBDWT_MASK0_WR(x, HW_MTBDWT_MASK0_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual MTBDWT_MASK0 bitfields
 */

/*!
 * @name Register MTBDWT_MASK0, field MASK[4:0] (RW)
 *
 * The value of the ignore mask, 0-31 bits, is applied to address range
 * matching. MASK = 0 is used to include all bits of the address in the comparison,
 * except if MASK = 0 and the comparator is configured to watch instruction fetch
 * addresses, address bit [0] is ignored by the hardware since all fetches must be at
 * least halfword aligned. For MASK != 0 and regardless of watch type, address
 * bits [x-1:0] are ignored in the address comparison. Using a mask means the
 * comparator matches on a range of addresses, defined by the unmasked most
 * significant bits of the address, bits [31:x]. The maximum MASK value is 24, producing a
 * 16 Mbyte mask. An attempted write of a MASK value > 24 is limited by the
 * MTBDWT hardware to 24. If MTBDWT_COMP0 is used as a data value comparator, then
 * MTBDWT_MASK0 should be programmed to zero.
 */
/*@{*/
#define BP_MTBDWT_MASK0_MASK (0U)          /*!< Bit position for MTBDWT_MASK0_MASK. */
#define BM_MTBDWT_MASK0_MASK (0x0000001FU) /*!< Bit mask for MTBDWT_MASK0_MASK. */
#define BS_MTBDWT_MASK0_MASK (5U)          /*!< Bit field size in bits for MTBDWT_MASK0_MASK. */

/*! @brief Read current value of the MTBDWT_MASK0_MASK field. */
#define BR_MTBDWT_MASK0_MASK(x) (HW_MTBDWT_MASK0(x).B.MASK)

/*! @brief Format value for bitfield MTBDWT_MASK0_MASK. */
#define BF_MTBDWT_MASK0_MASK(v) ((uint32_t)((uint32_t)(v) << BP_MTBDWT_MASK0_MASK) & BM_MTBDWT_MASK0_MASK)

/*! @brief Set the MASK field to a new value. */
#define BW_MTBDWT_MASK0_MASK(x, v) (HW_MTBDWT_MASK0_WR(x, (HW_MTBDWT_MASK0_RD(x) & ~BM_MTBDWT_MASK0_MASK) | BF_MTBDWT_MASK0_MASK(v)))
/*@}*/

/*******************************************************************************
 * HW_MTBDWT_FCT0 - MTB_DWT Comparator Function Register 0
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_FCT0 - MTB_DWT Comparator Function Register 0 (RW)
 *
 * Reset value: 0x00000000U
 *
 * The MTBDWT_FCTn registers control the operation of comparator n.
 */
typedef union _hw_mtbdwt_fct0
{
    uint32_t U;
    struct _hw_mtbdwt_fct0_bitfields
    {
        uint32_t FUNCTION : 4;         /*!< [3:0] Function */
        uint32_t RESERVED0 : 4;        /*!< [7:4]  */
        uint32_t DATAVMATCH : 1;       /*!< [8] Data Value Match */
        uint32_t RESERVED1 : 1;        /*!< [9]  */
        uint32_t DATAVSIZE : 2;        /*!< [11:10] Data Value Size */
        uint32_t DATAVADDR0 : 4;       /*!< [15:12] Data Value Address 0 */
        uint32_t RESERVED2 : 8;        /*!< [23:16]  */
        uint32_t MATCHED : 1;          /*!< [24] Comparator match */
        uint32_t RESERVED3 : 7;        /*!< [31:25]  */
    } B;
} hw_mtbdwt_fct0_t;

/*!
 * @name Constants and macros for entire MTBDWT_FCT0 register
 */
/*@{*/
#define HW_MTBDWT_FCT0_ADDR(x)   ((x) + 0x28U)

#define HW_MTBDWT_FCT0(x)        (*(__IO hw_mtbdwt_fct0_t *) HW_MTBDWT_FCT0_ADDR(x))
#define HW_MTBDWT_FCT0_RD(x)     (HW_MTBDWT_FCT0(x).U)
#define HW_MTBDWT_FCT0_WR(x, v)  (HW_MTBDWT_FCT0(x).U = (v))
#define HW_MTBDWT_FCT0_SET(x, v) (HW_MTBDWT_FCT0_WR(x, HW_MTBDWT_FCT0_RD(x) |  (v)))
#define HW_MTBDWT_FCT0_CLR(x, v) (HW_MTBDWT_FCT0_WR(x, HW_MTBDWT_FCT0_RD(x) & ~(v)))
#define HW_MTBDWT_FCT0_TOG(x, v) (HW_MTBDWT_FCT0_WR(x, HW_MTBDWT_FCT0_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual MTBDWT_FCT0 bitfields
 */

/*!
 * @name Register MTBDWT_FCT0, field FUNCTION[3:0] (RW)
 *
 * Selects the action taken on a comparator match. If MTBDWT_COMP0 is used for a
 * data value and MTBDWT_COMP1 for an address value, then MTBDWT_FCT1[FUNCTION]
 * must be set to zero. For this configuration, MTBDWT_MASK1 can be set to a
 * non-zero value, so the combined comparators match on a range of addresses.
 *
 * Values:
 * - 0000 - Disabled.
 * - 0100 - Instruction fetch.
 * - 0101 - Data operand read.
 * - 0110 - Data operand write.
 * - 0111 - Data operand (read + write).
 */
/*@{*/
#define BP_MTBDWT_FCT0_FUNCTION (0U)       /*!< Bit position for MTBDWT_FCT0_FUNCTION. */
#define BM_MTBDWT_FCT0_FUNCTION (0x0000000FU) /*!< Bit mask for MTBDWT_FCT0_FUNCTION. */
#define BS_MTBDWT_FCT0_FUNCTION (4U)       /*!< Bit field size in bits for MTBDWT_FCT0_FUNCTION. */

/*! @brief Read current value of the MTBDWT_FCT0_FUNCTION field. */
#define BR_MTBDWT_FCT0_FUNCTION(x) (HW_MTBDWT_FCT0(x).B.FUNCTION)

/*! @brief Format value for bitfield MTBDWT_FCT0_FUNCTION. */
#define BF_MTBDWT_FCT0_FUNCTION(v) ((uint32_t)((uint32_t)(v) << BP_MTBDWT_FCT0_FUNCTION) & BM_MTBDWT_FCT0_FUNCTION)

/*! @brief Set the FUNCTION field to a new value. */
#define BW_MTBDWT_FCT0_FUNCTION(x, v) (HW_MTBDWT_FCT0_WR(x, (HW_MTBDWT_FCT0_RD(x) & ~BM_MTBDWT_FCT0_FUNCTION) | BF_MTBDWT_FCT0_FUNCTION(v)))
/*@}*/

/*!
 * @name Register MTBDWT_FCT0, field DATAVMATCH[8] (RW)
 *
 * The assertion of this bit enables data value comparison. For this
 * implementation, MTBDWT_COMP0 supports address or data value comparisons; MTBDWT_COMP1
 * only supports address comparisons.
 *
 * Values:
 * - 0 - Perform address comparison.
 * - 1 - Perform data value comparison.
 */
/*@{*/
#define BP_MTBDWT_FCT0_DATAVMATCH (8U)     /*!< Bit position for MTBDWT_FCT0_DATAVMATCH. */
#define BM_MTBDWT_FCT0_DATAVMATCH (0x00000100U) /*!< Bit mask for MTBDWT_FCT0_DATAVMATCH. */
#define BS_MTBDWT_FCT0_DATAVMATCH (1U)     /*!< Bit field size in bits for MTBDWT_FCT0_DATAVMATCH. */

/*! @brief Read current value of the MTBDWT_FCT0_DATAVMATCH field. */
#define BR_MTBDWT_FCT0_DATAVMATCH(x) (HW_MTBDWT_FCT0(x).B.DATAVMATCH)

/*! @brief Format value for bitfield MTBDWT_FCT0_DATAVMATCH. */
#define BF_MTBDWT_FCT0_DATAVMATCH(v) ((uint32_t)((uint32_t)(v) << BP_MTBDWT_FCT0_DATAVMATCH) & BM_MTBDWT_FCT0_DATAVMATCH)

/*! @brief Set the DATAVMATCH field to a new value. */
#define BW_MTBDWT_FCT0_DATAVMATCH(x, v) (HW_MTBDWT_FCT0_WR(x, (HW_MTBDWT_FCT0_RD(x) & ~BM_MTBDWT_FCT0_DATAVMATCH) | BF_MTBDWT_FCT0_DATAVMATCH(v)))
/*@}*/

/*!
 * @name Register MTBDWT_FCT0, field DATAVSIZE[11:10] (RW)
 *
 * For data value matching, this field defines the size of the required data
 * comparison.
 *
 * Values:
 * - 00 - Byte.
 * - 01 - Halfword.
 * - 10 - Word.
 * - 11 - Reserved. Any attempts to use this value results in UNPREDICTABLE
 *     behavior.
 */
/*@{*/
#define BP_MTBDWT_FCT0_DATAVSIZE (10U)     /*!< Bit position for MTBDWT_FCT0_DATAVSIZE. */
#define BM_MTBDWT_FCT0_DATAVSIZE (0x00000C00U) /*!< Bit mask for MTBDWT_FCT0_DATAVSIZE. */
#define BS_MTBDWT_FCT0_DATAVSIZE (2U)      /*!< Bit field size in bits for MTBDWT_FCT0_DATAVSIZE. */

/*! @brief Read current value of the MTBDWT_FCT0_DATAVSIZE field. */
#define BR_MTBDWT_FCT0_DATAVSIZE(x) (HW_MTBDWT_FCT0(x).B.DATAVSIZE)

/*! @brief Format value for bitfield MTBDWT_FCT0_DATAVSIZE. */
#define BF_MTBDWT_FCT0_DATAVSIZE(v) ((uint32_t)((uint32_t)(v) << BP_MTBDWT_FCT0_DATAVSIZE) & BM_MTBDWT_FCT0_DATAVSIZE)

/*! @brief Set the DATAVSIZE field to a new value. */
#define BW_MTBDWT_FCT0_DATAVSIZE(x, v) (HW_MTBDWT_FCT0_WR(x, (HW_MTBDWT_FCT0_RD(x) & ~BM_MTBDWT_FCT0_DATAVSIZE) | BF_MTBDWT_FCT0_DATAVSIZE(v)))
/*@}*/

/*!
 * @name Register MTBDWT_FCT0, field DATAVADDR0[15:12] (RW)
 *
 * Since the MTB_DWT implements two comparators, the DATAVADDR0 field is
 * restricted to values {0,1}. When the DATAVMATCH bit is asserted, this field defines
 * the comparator number to use for linked address comparison. If MTBDWT_COMP0 is
 * used as a data watchpoint and MTBDWT_COMP1 as an address watchpoint,
 * DATAVADDR0 must be set.
 */
/*@{*/
#define BP_MTBDWT_FCT0_DATAVADDR0 (12U)    /*!< Bit position for MTBDWT_FCT0_DATAVADDR0. */
#define BM_MTBDWT_FCT0_DATAVADDR0 (0x0000F000U) /*!< Bit mask for MTBDWT_FCT0_DATAVADDR0. */
#define BS_MTBDWT_FCT0_DATAVADDR0 (4U)     /*!< Bit field size in bits for MTBDWT_FCT0_DATAVADDR0. */

/*! @brief Read current value of the MTBDWT_FCT0_DATAVADDR0 field. */
#define BR_MTBDWT_FCT0_DATAVADDR0(x) (HW_MTBDWT_FCT0(x).B.DATAVADDR0)

/*! @brief Format value for bitfield MTBDWT_FCT0_DATAVADDR0. */
#define BF_MTBDWT_FCT0_DATAVADDR0(v) ((uint32_t)((uint32_t)(v) << BP_MTBDWT_FCT0_DATAVADDR0) & BM_MTBDWT_FCT0_DATAVADDR0)

/*! @brief Set the DATAVADDR0 field to a new value. */
#define BW_MTBDWT_FCT0_DATAVADDR0(x, v) (HW_MTBDWT_FCT0_WR(x, (HW_MTBDWT_FCT0_RD(x) & ~BM_MTBDWT_FCT0_DATAVADDR0) | BF_MTBDWT_FCT0_DATAVADDR0(v)))
/*@}*/

/*!
 * @name Register MTBDWT_FCT0, field MATCHED[24] (RO)
 *
 * If this read-only flag is asserted, it indicates the operation defined by the
 * FUNCTION field occurred since the last read of the register. Reading the
 * register clears this bit.
 *
 * Values:
 * - 0 - No match.
 * - 1 - Match occurred.
 */
/*@{*/
#define BP_MTBDWT_FCT0_MATCHED (24U)       /*!< Bit position for MTBDWT_FCT0_MATCHED. */
#define BM_MTBDWT_FCT0_MATCHED (0x01000000U) /*!< Bit mask for MTBDWT_FCT0_MATCHED. */
#define BS_MTBDWT_FCT0_MATCHED (1U)        /*!< Bit field size in bits for MTBDWT_FCT0_MATCHED. */

/*! @brief Read current value of the MTBDWT_FCT0_MATCHED field. */
#define BR_MTBDWT_FCT0_MATCHED(x) (HW_MTBDWT_FCT0(x).B.MATCHED)
/*@}*/

/*******************************************************************************
 * HW_MTBDWT_COMP1 - MTB_DWT Comparator Register
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_COMP1 - MTB_DWT Comparator Register (RW)
 *
 * Reset value: 0x00000000U
 *
 * The MTBDWT_COMPn registers provide the reference value for comparator n.
 */
typedef union _hw_mtbdwt_comp1
{
    uint32_t U;
    struct _hw_mtbdwt_comp1_bitfields
    {
        uint32_t COMP : 32;            /*!< [31:0] Reference value for comparison */
    } B;
} hw_mtbdwt_comp1_t;

/*!
 * @name Constants and macros for entire MTBDWT_COMP1 register
 */
/*@{*/
#define HW_MTBDWT_COMP1_ADDR(x)  ((x) + 0x30U)

#define HW_MTBDWT_COMP1(x)       (*(__IO hw_mtbdwt_comp1_t *) HW_MTBDWT_COMP1_ADDR(x))
#define HW_MTBDWT_COMP1_RD(x)    (HW_MTBDWT_COMP1(x).U)
#define HW_MTBDWT_COMP1_WR(x, v) (HW_MTBDWT_COMP1(x).U = (v))
#define HW_MTBDWT_COMP1_SET(x, v) (HW_MTBDWT_COMP1_WR(x, HW_MTBDWT_COMP1_RD(x) |  (v)))
#define HW_MTBDWT_COMP1_CLR(x, v) (HW_MTBDWT_COMP1_WR(x, HW_MTBDWT_COMP1_RD(x) & ~(v)))
#define HW_MTBDWT_COMP1_TOG(x, v) (HW_MTBDWT_COMP1_WR(x, HW_MTBDWT_COMP1_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual MTBDWT_COMP1 bitfields
 */

/*!
 * @name Register MTBDWT_COMP1, field COMP[31:0] (RW)
 *
 * If MTBDWT_COMP0 is used for a data value comparator and the access size is
 * byte or halfword, the data value must be replicated across all appropriate byte
 * lanes of this register. For example, if the data is a byte-sized "x" value,
 * then COMP[31:24] = COMP[23:16] = COMP[15:8] = COMP[7:0] = "x". Likewise, if the
 * data is a halfword-size "y" value, then COMP[31:16] = COMP[15:0] = "y".
 */
/*@{*/
#define BP_MTBDWT_COMP1_COMP (0U)          /*!< Bit position for MTBDWT_COMP1_COMP. */
#define BM_MTBDWT_COMP1_COMP (0xFFFFFFFFU) /*!< Bit mask for MTBDWT_COMP1_COMP. */
#define BS_MTBDWT_COMP1_COMP (32U)         /*!< Bit field size in bits for MTBDWT_COMP1_COMP. */

/*! @brief Read current value of the MTBDWT_COMP1_COMP field. */
#define BR_MTBDWT_COMP1_COMP(x) (HW_MTBDWT_COMP1(x).U)

/*! @brief Format value for bitfield MTBDWT_COMP1_COMP. */
#define BF_MTBDWT_COMP1_COMP(v) ((uint32_t)((uint32_t)(v) << BP_MTBDWT_COMP1_COMP) & BM_MTBDWT_COMP1_COMP)

/*! @brief Set the COMP field to a new value. */
#define BW_MTBDWT_COMP1_COMP(x, v) (HW_MTBDWT_COMP1_WR(x, v))
/*@}*/

/*******************************************************************************
 * HW_MTBDWT_MASK1 - MTB_DWT Comparator Mask Register
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_MASK1 - MTB_DWT Comparator Mask Register (RW)
 *
 * Reset value: 0x00000000U
 *
 * The MTBDWT_MASKn registers define the size of the ignore mask applied to the
 * reference address for address range matching by comparator n. Note the format
 * of this mask field is different than the MTB_MASTER[MASK].
 */
typedef union _hw_mtbdwt_mask1
{
    uint32_t U;
    struct _hw_mtbdwt_mask1_bitfields
    {
        uint32_t MASK : 5;             /*!< [4:0] MASK */
        uint32_t RESERVED0 : 27;       /*!< [31:5]  */
    } B;
} hw_mtbdwt_mask1_t;

/*!
 * @name Constants and macros for entire MTBDWT_MASK1 register
 */
/*@{*/
#define HW_MTBDWT_MASK1_ADDR(x)  ((x) + 0x34U)

#define HW_MTBDWT_MASK1(x)       (*(__IO hw_mtbdwt_mask1_t *) HW_MTBDWT_MASK1_ADDR(x))
#define HW_MTBDWT_MASK1_RD(x)    (HW_MTBDWT_MASK1(x).U)
#define HW_MTBDWT_MASK1_WR(x, v) (HW_MTBDWT_MASK1(x).U = (v))
#define HW_MTBDWT_MASK1_SET(x, v) (HW_MTBDWT_MASK1_WR(x, HW_MTBDWT_MASK1_RD(x) |  (v)))
#define HW_MTBDWT_MASK1_CLR(x, v) (HW_MTBDWT_MASK1_WR(x, HW_MTBDWT_MASK1_RD(x) & ~(v)))
#define HW_MTBDWT_MASK1_TOG(x, v) (HW_MTBDWT_MASK1_WR(x, HW_MTBDWT_MASK1_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual MTBDWT_MASK1 bitfields
 */

/*!
 * @name Register MTBDWT_MASK1, field MASK[4:0] (RW)
 *
 * The value of the ignore mask, 0-31 bits, is applied to address range
 * matching. MASK = 0 is used to include all bits of the address in the comparison,
 * except if MASK = 0 and the comparator is configured to watch instruction fetch
 * addresses, address bit [0] is ignored by the hardware since all fetches must be at
 * least halfword aligned. For MASK != 0 and regardless of watch type, address
 * bits [x-1:0] are ignored in the address comparison. Using a mask means the
 * comparator matches on a range of addresses, defined by the unmasked most
 * significant bits of the address, bits [31:x]. The maximum MASK value is 24, producing a
 * 16 Mbyte mask. An attempted write of a MASK value > 24 is limited by the
 * MTBDWT hardware to 24. If MTBDWT_COMP0 is used as a data value comparator, then
 * MTBDWT_MASK0 should be programmed to zero.
 */
/*@{*/
#define BP_MTBDWT_MASK1_MASK (0U)          /*!< Bit position for MTBDWT_MASK1_MASK. */
#define BM_MTBDWT_MASK1_MASK (0x0000001FU) /*!< Bit mask for MTBDWT_MASK1_MASK. */
#define BS_MTBDWT_MASK1_MASK (5U)          /*!< Bit field size in bits for MTBDWT_MASK1_MASK. */

/*! @brief Read current value of the MTBDWT_MASK1_MASK field. */
#define BR_MTBDWT_MASK1_MASK(x) (HW_MTBDWT_MASK1(x).B.MASK)

/*! @brief Format value for bitfield MTBDWT_MASK1_MASK. */
#define BF_MTBDWT_MASK1_MASK(v) ((uint32_t)((uint32_t)(v) << BP_MTBDWT_MASK1_MASK) & BM_MTBDWT_MASK1_MASK)

/*! @brief Set the MASK field to a new value. */
#define BW_MTBDWT_MASK1_MASK(x, v) (HW_MTBDWT_MASK1_WR(x, (HW_MTBDWT_MASK1_RD(x) & ~BM_MTBDWT_MASK1_MASK) | BF_MTBDWT_MASK1_MASK(v)))
/*@}*/

/*******************************************************************************
 * HW_MTBDWT_FCT1 - MTB_DWT Comparator Function Register 1
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_FCT1 - MTB_DWT Comparator Function Register 1 (RW)
 *
 * Reset value: 0x00000000U
 *
 * The MTBDWT_FCTn registers control the operation of comparator n. Since the
 * MTB_DWT only supports data value comparisons on comparator 0, there are several
 * fields in the MTBDWT_FCT1 register that are RAZ/WI (bits 12, 11:10, 8).
 */
typedef union _hw_mtbdwt_fct1
{
    uint32_t U;
    struct _hw_mtbdwt_fct1_bitfields
    {
        uint32_t FUNCTION : 4;         /*!< [3:0] Function */
        uint32_t RESERVED0 : 20;       /*!< [23:4]  */
        uint32_t MATCHED : 1;          /*!< [24] Comparator match */
        uint32_t RESERVED1 : 7;        /*!< [31:25]  */
    } B;
} hw_mtbdwt_fct1_t;

/*!
 * @name Constants and macros for entire MTBDWT_FCT1 register
 */
/*@{*/
#define HW_MTBDWT_FCT1_ADDR(x)   ((x) + 0x38U)

#define HW_MTBDWT_FCT1(x)        (*(__IO hw_mtbdwt_fct1_t *) HW_MTBDWT_FCT1_ADDR(x))
#define HW_MTBDWT_FCT1_RD(x)     (HW_MTBDWT_FCT1(x).U)
#define HW_MTBDWT_FCT1_WR(x, v)  (HW_MTBDWT_FCT1(x).U = (v))
#define HW_MTBDWT_FCT1_SET(x, v) (HW_MTBDWT_FCT1_WR(x, HW_MTBDWT_FCT1_RD(x) |  (v)))
#define HW_MTBDWT_FCT1_CLR(x, v) (HW_MTBDWT_FCT1_WR(x, HW_MTBDWT_FCT1_RD(x) & ~(v)))
#define HW_MTBDWT_FCT1_TOG(x, v) (HW_MTBDWT_FCT1_WR(x, HW_MTBDWT_FCT1_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual MTBDWT_FCT1 bitfields
 */

/*!
 * @name Register MTBDWT_FCT1, field FUNCTION[3:0] (RW)
 *
 * Selects the action taken on a comparator match. If MTBDWT_COMP0 is used for a
 * data value and MTBDWT_COMP1 for an address value, then MTBDWT_FCT1[FUNCTION]
 * must be set to zero. For this configuration, MTBDWT_MASK1 can be set to a
 * non-zero value, so the combined comparators match on a range of addresses.
 *
 * Values:
 * - 0000 - Disabled.
 * - 0100 - Instruction fetch.
 * - 0101 - Data operand read.
 * - 0110 - Data operand write.
 * - 0111 - Data operand (read + write).
 */
/*@{*/
#define BP_MTBDWT_FCT1_FUNCTION (0U)       /*!< Bit position for MTBDWT_FCT1_FUNCTION. */
#define BM_MTBDWT_FCT1_FUNCTION (0x0000000FU) /*!< Bit mask for MTBDWT_FCT1_FUNCTION. */
#define BS_MTBDWT_FCT1_FUNCTION (4U)       /*!< Bit field size in bits for MTBDWT_FCT1_FUNCTION. */

/*! @brief Read current value of the MTBDWT_FCT1_FUNCTION field. */
#define BR_MTBDWT_FCT1_FUNCTION(x) (HW_MTBDWT_FCT1(x).B.FUNCTION)

/*! @brief Format value for bitfield MTBDWT_FCT1_FUNCTION. */
#define BF_MTBDWT_FCT1_FUNCTION(v) ((uint32_t)((uint32_t)(v) << BP_MTBDWT_FCT1_FUNCTION) & BM_MTBDWT_FCT1_FUNCTION)

/*! @brief Set the FUNCTION field to a new value. */
#define BW_MTBDWT_FCT1_FUNCTION(x, v) (HW_MTBDWT_FCT1_WR(x, (HW_MTBDWT_FCT1_RD(x) & ~BM_MTBDWT_FCT1_FUNCTION) | BF_MTBDWT_FCT1_FUNCTION(v)))
/*@}*/

/*!
 * @name Register MTBDWT_FCT1, field MATCHED[24] (RO)
 *
 * If this read-only flag is asserted, it indicates the operation defined by the
 * FUNCTION field occurred since the last read of the register. Reading the
 * register clears this bit.
 *
 * Values:
 * - 0 - No match.
 * - 1 - Match occurred.
 */
/*@{*/
#define BP_MTBDWT_FCT1_MATCHED (24U)       /*!< Bit position for MTBDWT_FCT1_MATCHED. */
#define BM_MTBDWT_FCT1_MATCHED (0x01000000U) /*!< Bit mask for MTBDWT_FCT1_MATCHED. */
#define BS_MTBDWT_FCT1_MATCHED (1U)        /*!< Bit field size in bits for MTBDWT_FCT1_MATCHED. */

/*! @brief Read current value of the MTBDWT_FCT1_MATCHED field. */
#define BR_MTBDWT_FCT1_MATCHED(x) (HW_MTBDWT_FCT1(x).B.MATCHED)
/*@}*/

/*******************************************************************************
 * HW_MTBDWT_TBCTRL - MTB_DWT Trace Buffer Control Register
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_TBCTRL - MTB_DWT Trace Buffer Control Register (RW)
 *
 * Reset value: 0x20000000U
 *
 * The MTBDWT_TBCTRL register defines how the watchpoint comparisons control the
 * actual trace buffer operation. Recall the MTB supports starting and stopping
 * the program trace based on the watchpoint comparisons signaled via TSTART and
 * TSTOP. The watchpoint comparison signals are enabled in the MTB's control
 * logic by setting the appropriate enable bits, MTB_MASTER[TSTARTEN, TSTOPEN]. In
 * the event of simultaneous assertion of both TSTART and TSTOP, TSTART takes
 * priority.
 */
typedef union _hw_mtbdwt_tbctrl
{
    uint32_t U;
    struct _hw_mtbdwt_tbctrl_bitfields
    {
        uint32_t ACOMP0 : 1;           /*!< [0] Action based on Comparator 0 match */
        uint32_t ACOMP1 : 1;           /*!< [1] Action based on Comparator 1 match */
        uint32_t RESERVED0 : 26;       /*!< [27:2]  */
        uint32_t NUMCOMP : 4;          /*!< [31:28] Number of Comparators */
    } B;
} hw_mtbdwt_tbctrl_t;

/*!
 * @name Constants and macros for entire MTBDWT_TBCTRL register
 */
/*@{*/
#define HW_MTBDWT_TBCTRL_ADDR(x) ((x) + 0x200U)

#define HW_MTBDWT_TBCTRL(x)      (*(__IO hw_mtbdwt_tbctrl_t *) HW_MTBDWT_TBCTRL_ADDR(x))
#define HW_MTBDWT_TBCTRL_RD(x)   (HW_MTBDWT_TBCTRL(x).U)
#define HW_MTBDWT_TBCTRL_WR(x, v) (HW_MTBDWT_TBCTRL(x).U = (v))
#define HW_MTBDWT_TBCTRL_SET(x, v) (HW_MTBDWT_TBCTRL_WR(x, HW_MTBDWT_TBCTRL_RD(x) |  (v)))
#define HW_MTBDWT_TBCTRL_CLR(x, v) (HW_MTBDWT_TBCTRL_WR(x, HW_MTBDWT_TBCTRL_RD(x) & ~(v)))
#define HW_MTBDWT_TBCTRL_TOG(x, v) (HW_MTBDWT_TBCTRL_WR(x, HW_MTBDWT_TBCTRL_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual MTBDWT_TBCTRL bitfields
 */

/*!
 * @name Register MTBDWT_TBCTRL, field ACOMP0[0] (RW)
 *
 * When the MTBDWT_FCT0[MATCHED] is set, it indicates MTBDWT_COMP0 address
 * compare has triggered and the trace buffer's recording state is changed. The
 * assertion of MTBDWT_FCT0[MATCHED] is caused by the following conditions: Address
 * match in MTBDWT_COMP0 when MTBDWT_FCT0[DATAVMATCH] = 0 Data match in MTBDWT_COMP0
 * when MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] = {1,0} Data match in MTBDWT_COMP0
 * and address match in MTBDWT_COMP1 when MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] =
 * {1,1}
 *
 * Values:
 * - 0 - Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].
 * - 1 - Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].
 */
/*@{*/
#define BP_MTBDWT_TBCTRL_ACOMP0 (0U)       /*!< Bit position for MTBDWT_TBCTRL_ACOMP0. */
#define BM_MTBDWT_TBCTRL_ACOMP0 (0x00000001U) /*!< Bit mask for MTBDWT_TBCTRL_ACOMP0. */
#define BS_MTBDWT_TBCTRL_ACOMP0 (1U)       /*!< Bit field size in bits for MTBDWT_TBCTRL_ACOMP0. */

/*! @brief Read current value of the MTBDWT_TBCTRL_ACOMP0 field. */
#define BR_MTBDWT_TBCTRL_ACOMP0(x) (HW_MTBDWT_TBCTRL(x).B.ACOMP0)

/*! @brief Format value for bitfield MTBDWT_TBCTRL_ACOMP0. */
#define BF_MTBDWT_TBCTRL_ACOMP0(v) ((uint32_t)((uint32_t)(v) << BP_MTBDWT_TBCTRL_ACOMP0) & BM_MTBDWT_TBCTRL_ACOMP0)

/*! @brief Set the ACOMP0 field to a new value. */
#define BW_MTBDWT_TBCTRL_ACOMP0(x, v) (HW_MTBDWT_TBCTRL_WR(x, (HW_MTBDWT_TBCTRL_RD(x) & ~BM_MTBDWT_TBCTRL_ACOMP0) | BF_MTBDWT_TBCTRL_ACOMP0(v)))
/*@}*/

/*!
 * @name Register MTBDWT_TBCTRL, field ACOMP1[1] (RW)
 *
 * When the MTBDWT_FCT1[MATCHED] is set, it indicates MTBDWT_COMP1 address
 * compare has triggered and the trace buffer's recording state is changed.
 *
 * Values:
 * - 0 - Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].
 * - 1 - Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].
 */
/*@{*/
#define BP_MTBDWT_TBCTRL_ACOMP1 (1U)       /*!< Bit position for MTBDWT_TBCTRL_ACOMP1. */
#define BM_MTBDWT_TBCTRL_ACOMP1 (0x00000002U) /*!< Bit mask for MTBDWT_TBCTRL_ACOMP1. */
#define BS_MTBDWT_TBCTRL_ACOMP1 (1U)       /*!< Bit field size in bits for MTBDWT_TBCTRL_ACOMP1. */

/*! @brief Read current value of the MTBDWT_TBCTRL_ACOMP1 field. */
#define BR_MTBDWT_TBCTRL_ACOMP1(x) (HW_MTBDWT_TBCTRL(x).B.ACOMP1)

/*! @brief Format value for bitfield MTBDWT_TBCTRL_ACOMP1. */
#define BF_MTBDWT_TBCTRL_ACOMP1(v) ((uint32_t)((uint32_t)(v) << BP_MTBDWT_TBCTRL_ACOMP1) & BM_MTBDWT_TBCTRL_ACOMP1)

/*! @brief Set the ACOMP1 field to a new value. */
#define BW_MTBDWT_TBCTRL_ACOMP1(x, v) (HW_MTBDWT_TBCTRL_WR(x, (HW_MTBDWT_TBCTRL_RD(x) & ~BM_MTBDWT_TBCTRL_ACOMP1) | BF_MTBDWT_TBCTRL_ACOMP1(v)))
/*@}*/

/*!
 * @name Register MTBDWT_TBCTRL, field NUMCOMP[31:28] (RO)
 *
 * This read-only field specifies the number of comparators in the MTB_DWT. This
 * implementation includes two registers.
 */
/*@{*/
#define BP_MTBDWT_TBCTRL_NUMCOMP (28U)     /*!< Bit position for MTBDWT_TBCTRL_NUMCOMP. */
#define BM_MTBDWT_TBCTRL_NUMCOMP (0xF0000000U) /*!< Bit mask for MTBDWT_TBCTRL_NUMCOMP. */
#define BS_MTBDWT_TBCTRL_NUMCOMP (4U)      /*!< Bit field size in bits for MTBDWT_TBCTRL_NUMCOMP. */

/*! @brief Read current value of the MTBDWT_TBCTRL_NUMCOMP field. */
#define BR_MTBDWT_TBCTRL_NUMCOMP(x) (HW_MTBDWT_TBCTRL(x).B.NUMCOMP)
/*@}*/

/*******************************************************************************
 * HW_MTBDWT_DEVICECFG - Device Configuration Register
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_DEVICECFG - Device Configuration Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * This register indicates the device configuration. It is hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtbdwt_devicecfg
{
    uint32_t U;
    struct _hw_mtbdwt_devicecfg_bitfields
    {
        uint32_t DEVICECFG : 32;       /*!< [31:0]  */
    } B;
} hw_mtbdwt_devicecfg_t;

/*!
 * @name Constants and macros for entire MTBDWT_DEVICECFG register
 */
/*@{*/
#define HW_MTBDWT_DEVICECFG_ADDR(x) ((x) + 0xFC8U)

#define HW_MTBDWT_DEVICECFG(x)   (*(__I hw_mtbdwt_devicecfg_t *) HW_MTBDWT_DEVICECFG_ADDR(x))
#define HW_MTBDWT_DEVICECFG_RD(x) (HW_MTBDWT_DEVICECFG(x).U)
/*@}*/

/*
 * Constants & macros for individual MTBDWT_DEVICECFG bitfields
 */

/*!
 * @name Register MTBDWT_DEVICECFG, field DEVICECFG[31:0] (RO)
 *
 * Hardwired to 0x0000_0000.
 */
/*@{*/
#define BP_MTBDWT_DEVICECFG_DEVICECFG (0U) /*!< Bit position for MTBDWT_DEVICECFG_DEVICECFG. */
#define BM_MTBDWT_DEVICECFG_DEVICECFG (0xFFFFFFFFU) /*!< Bit mask for MTBDWT_DEVICECFG_DEVICECFG. */
#define BS_MTBDWT_DEVICECFG_DEVICECFG (32U) /*!< Bit field size in bits for MTBDWT_DEVICECFG_DEVICECFG. */

/*! @brief Read current value of the MTBDWT_DEVICECFG_DEVICECFG field. */
#define BR_MTBDWT_DEVICECFG_DEVICECFG(x) (HW_MTBDWT_DEVICECFG(x).U)
/*@}*/

/*******************************************************************************
 * HW_MTBDWT_DEVICETYPID - Device Type Identifier Register
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_DEVICETYPID - Device Type Identifier Register (RO)
 *
 * Reset value: 0x00000004U
 *
 * This register indicates the device type ID. It is hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtbdwt_devicetypid
{
    uint32_t U;
    struct _hw_mtbdwt_devicetypid_bitfields
    {
        uint32_t DEVICETYPID : 32;     /*!< [31:0]  */
    } B;
} hw_mtbdwt_devicetypid_t;

/*!
 * @name Constants and macros for entire MTBDWT_DEVICETYPID register
 */
/*@{*/
#define HW_MTBDWT_DEVICETYPID_ADDR(x) ((x) + 0xFCCU)

#define HW_MTBDWT_DEVICETYPID(x) (*(__I hw_mtbdwt_devicetypid_t *) HW_MTBDWT_DEVICETYPID_ADDR(x))
#define HW_MTBDWT_DEVICETYPID_RD(x) (HW_MTBDWT_DEVICETYPID(x).U)
/*@}*/

/*
 * Constants & macros for individual MTBDWT_DEVICETYPID bitfields
 */

/*!
 * @name Register MTBDWT_DEVICETYPID, field DEVICETYPID[31:0] (RO)
 *
 * Hardwired to 0x0000_0004.
 */
/*@{*/
#define BP_MTBDWT_DEVICETYPID_DEVICETYPID (0U) /*!< Bit position for MTBDWT_DEVICETYPID_DEVICETYPID. */
#define BM_MTBDWT_DEVICETYPID_DEVICETYPID (0xFFFFFFFFU) /*!< Bit mask for MTBDWT_DEVICETYPID_DEVICETYPID. */
#define BS_MTBDWT_DEVICETYPID_DEVICETYPID (32U) /*!< Bit field size in bits for MTBDWT_DEVICETYPID_DEVICETYPID. */

/*! @brief Read current value of the MTBDWT_DEVICETYPID_DEVICETYPID field. */
#define BR_MTBDWT_DEVICETYPID_DEVICETYPID(x) (HW_MTBDWT_DEVICETYPID(x).U)
/*@}*/

/*******************************************************************************
 * HW_MTBDWT_PERIPHID4 - Peripheral ID Register
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_PERIPHID4 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtbdwt_periphid4
{
    uint32_t U;
    struct _hw_mtbdwt_periphid4_bitfields
    {
        uint32_t PERIPHID : 32;        /*!< [31:0]  */
    } B;
} hw_mtbdwt_periphid4_t;

/*!
 * @name Constants and macros for entire MTBDWT_PERIPHID4 register
 */
/*@{*/
#define HW_MTBDWT_PERIPHID4_ADDR(x) ((x) + 0xFD0U)

#define HW_MTBDWT_PERIPHID4(x)   (*(__I hw_mtbdwt_periphid4_t *) HW_MTBDWT_PERIPHID4_ADDR(x))
#define HW_MTBDWT_PERIPHID4_RD(x) (HW_MTBDWT_PERIPHID4(x).U)
/*@}*/

/*
 * Constants & macros for individual MTBDWT_PERIPHID4 bitfields
 */

/*!
 * @name Register MTBDWT_PERIPHID4, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
/*@{*/
#define BP_MTBDWT_PERIPHID4_PERIPHID (0U)  /*!< Bit position for MTBDWT_PERIPHID4_PERIPHID. */
#define BM_MTBDWT_PERIPHID4_PERIPHID (0xFFFFFFFFU) /*!< Bit mask for MTBDWT_PERIPHID4_PERIPHID. */
#define BS_MTBDWT_PERIPHID4_PERIPHID (32U) /*!< Bit field size in bits for MTBDWT_PERIPHID4_PERIPHID. */

/*! @brief Read current value of the MTBDWT_PERIPHID4_PERIPHID field. */
#define BR_MTBDWT_PERIPHID4_PERIPHID(x) (HW_MTBDWT_PERIPHID4(x).U)
/*@}*/
/*******************************************************************************
 * HW_MTBDWT_PERIPHID5 - Peripheral ID Register
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_PERIPHID5 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtbdwt_periphid5
{
    uint32_t U;
    struct _hw_mtbdwt_periphid5_bitfields
    {
        uint32_t PERIPHID : 32;        /*!< [31:0]  */
    } B;
} hw_mtbdwt_periphid5_t;

/*!
 * @name Constants and macros for entire MTBDWT_PERIPHID5 register
 */
/*@{*/
#define HW_MTBDWT_PERIPHID5_ADDR(x) ((x) + 0xFD4U)

#define HW_MTBDWT_PERIPHID5(x)   (*(__I hw_mtbdwt_periphid5_t *) HW_MTBDWT_PERIPHID5_ADDR(x))
#define HW_MTBDWT_PERIPHID5_RD(x) (HW_MTBDWT_PERIPHID5(x).U)
/*@}*/

/*
 * Constants & macros for individual MTBDWT_PERIPHID5 bitfields
 */

/*!
 * @name Register MTBDWT_PERIPHID5, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
/*@{*/
#define BP_MTBDWT_PERIPHID5_PERIPHID (0U)  /*!< Bit position for MTBDWT_PERIPHID5_PERIPHID. */
#define BM_MTBDWT_PERIPHID5_PERIPHID (0xFFFFFFFFU) /*!< Bit mask for MTBDWT_PERIPHID5_PERIPHID. */
#define BS_MTBDWT_PERIPHID5_PERIPHID (32U) /*!< Bit field size in bits for MTBDWT_PERIPHID5_PERIPHID. */

/*! @brief Read current value of the MTBDWT_PERIPHID5_PERIPHID field. */
#define BR_MTBDWT_PERIPHID5_PERIPHID(x) (HW_MTBDWT_PERIPHID5(x).U)
/*@}*/
/*******************************************************************************
 * HW_MTBDWT_PERIPHID6 - Peripheral ID Register
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_PERIPHID6 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtbdwt_periphid6
{
    uint32_t U;
    struct _hw_mtbdwt_periphid6_bitfields
    {
        uint32_t PERIPHID : 32;        /*!< [31:0]  */
    } B;
} hw_mtbdwt_periphid6_t;

/*!
 * @name Constants and macros for entire MTBDWT_PERIPHID6 register
 */
/*@{*/
#define HW_MTBDWT_PERIPHID6_ADDR(x) ((x) + 0xFD8U)

#define HW_MTBDWT_PERIPHID6(x)   (*(__I hw_mtbdwt_periphid6_t *) HW_MTBDWT_PERIPHID6_ADDR(x))
#define HW_MTBDWT_PERIPHID6_RD(x) (HW_MTBDWT_PERIPHID6(x).U)
/*@}*/

/*
 * Constants & macros for individual MTBDWT_PERIPHID6 bitfields
 */

/*!
 * @name Register MTBDWT_PERIPHID6, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
/*@{*/
#define BP_MTBDWT_PERIPHID6_PERIPHID (0U)  /*!< Bit position for MTBDWT_PERIPHID6_PERIPHID. */
#define BM_MTBDWT_PERIPHID6_PERIPHID (0xFFFFFFFFU) /*!< Bit mask for MTBDWT_PERIPHID6_PERIPHID. */
#define BS_MTBDWT_PERIPHID6_PERIPHID (32U) /*!< Bit field size in bits for MTBDWT_PERIPHID6_PERIPHID. */

/*! @brief Read current value of the MTBDWT_PERIPHID6_PERIPHID field. */
#define BR_MTBDWT_PERIPHID6_PERIPHID(x) (HW_MTBDWT_PERIPHID6(x).U)
/*@}*/
/*******************************************************************************
 * HW_MTBDWT_PERIPHID7 - Peripheral ID Register
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_PERIPHID7 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtbdwt_periphid7
{
    uint32_t U;
    struct _hw_mtbdwt_periphid7_bitfields
    {
        uint32_t PERIPHID : 32;        /*!< [31:0]  */
    } B;
} hw_mtbdwt_periphid7_t;

/*!
 * @name Constants and macros for entire MTBDWT_PERIPHID7 register
 */
/*@{*/
#define HW_MTBDWT_PERIPHID7_ADDR(x) ((x) + 0xFDCU)

#define HW_MTBDWT_PERIPHID7(x)   (*(__I hw_mtbdwt_periphid7_t *) HW_MTBDWT_PERIPHID7_ADDR(x))
#define HW_MTBDWT_PERIPHID7_RD(x) (HW_MTBDWT_PERIPHID7(x).U)
/*@}*/

/*
 * Constants & macros for individual MTBDWT_PERIPHID7 bitfields
 */

/*!
 * @name Register MTBDWT_PERIPHID7, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
/*@{*/
#define BP_MTBDWT_PERIPHID7_PERIPHID (0U)  /*!< Bit position for MTBDWT_PERIPHID7_PERIPHID. */
#define BM_MTBDWT_PERIPHID7_PERIPHID (0xFFFFFFFFU) /*!< Bit mask for MTBDWT_PERIPHID7_PERIPHID. */
#define BS_MTBDWT_PERIPHID7_PERIPHID (32U) /*!< Bit field size in bits for MTBDWT_PERIPHID7_PERIPHID. */

/*! @brief Read current value of the MTBDWT_PERIPHID7_PERIPHID field. */
#define BR_MTBDWT_PERIPHID7_PERIPHID(x) (HW_MTBDWT_PERIPHID7(x).U)
/*@}*/
/*******************************************************************************
 * HW_MTBDWT_PERIPHID0 - Peripheral ID Register
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_PERIPHID0 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtbdwt_periphid0
{
    uint32_t U;
    struct _hw_mtbdwt_periphid0_bitfields
    {
        uint32_t PERIPHID : 32;        /*!< [31:0]  */
    } B;
} hw_mtbdwt_periphid0_t;

/*!
 * @name Constants and macros for entire MTBDWT_PERIPHID0 register
 */
/*@{*/
#define HW_MTBDWT_PERIPHID0_ADDR(x) ((x) + 0xFE0U)

#define HW_MTBDWT_PERIPHID0(x)   (*(__I hw_mtbdwt_periphid0_t *) HW_MTBDWT_PERIPHID0_ADDR(x))
#define HW_MTBDWT_PERIPHID0_RD(x) (HW_MTBDWT_PERIPHID0(x).U)
/*@}*/

/*
 * Constants & macros for individual MTBDWT_PERIPHID0 bitfields
 */

/*!
 * @name Register MTBDWT_PERIPHID0, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
/*@{*/
#define BP_MTBDWT_PERIPHID0_PERIPHID (0U)  /*!< Bit position for MTBDWT_PERIPHID0_PERIPHID. */
#define BM_MTBDWT_PERIPHID0_PERIPHID (0xFFFFFFFFU) /*!< Bit mask for MTBDWT_PERIPHID0_PERIPHID. */
#define BS_MTBDWT_PERIPHID0_PERIPHID (32U) /*!< Bit field size in bits for MTBDWT_PERIPHID0_PERIPHID. */

/*! @brief Read current value of the MTBDWT_PERIPHID0_PERIPHID field. */
#define BR_MTBDWT_PERIPHID0_PERIPHID(x) (HW_MTBDWT_PERIPHID0(x).U)
/*@}*/
/*******************************************************************************
 * HW_MTBDWT_PERIPHID1 - Peripheral ID Register
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_PERIPHID1 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtbdwt_periphid1
{
    uint32_t U;
    struct _hw_mtbdwt_periphid1_bitfields
    {
        uint32_t PERIPHID : 32;        /*!< [31:0]  */
    } B;
} hw_mtbdwt_periphid1_t;

/*!
 * @name Constants and macros for entire MTBDWT_PERIPHID1 register
 */
/*@{*/
#define HW_MTBDWT_PERIPHID1_ADDR(x) ((x) + 0xFE4U)

#define HW_MTBDWT_PERIPHID1(x)   (*(__I hw_mtbdwt_periphid1_t *) HW_MTBDWT_PERIPHID1_ADDR(x))
#define HW_MTBDWT_PERIPHID1_RD(x) (HW_MTBDWT_PERIPHID1(x).U)
/*@}*/

/*
 * Constants & macros for individual MTBDWT_PERIPHID1 bitfields
 */

/*!
 * @name Register MTBDWT_PERIPHID1, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
/*@{*/
#define BP_MTBDWT_PERIPHID1_PERIPHID (0U)  /*!< Bit position for MTBDWT_PERIPHID1_PERIPHID. */
#define BM_MTBDWT_PERIPHID1_PERIPHID (0xFFFFFFFFU) /*!< Bit mask for MTBDWT_PERIPHID1_PERIPHID. */
#define BS_MTBDWT_PERIPHID1_PERIPHID (32U) /*!< Bit field size in bits for MTBDWT_PERIPHID1_PERIPHID. */

/*! @brief Read current value of the MTBDWT_PERIPHID1_PERIPHID field. */
#define BR_MTBDWT_PERIPHID1_PERIPHID(x) (HW_MTBDWT_PERIPHID1(x).U)
/*@}*/
/*******************************************************************************
 * HW_MTBDWT_PERIPHID2 - Peripheral ID Register
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_PERIPHID2 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtbdwt_periphid2
{
    uint32_t U;
    struct _hw_mtbdwt_periphid2_bitfields
    {
        uint32_t PERIPHID : 32;        /*!< [31:0]  */
    } B;
} hw_mtbdwt_periphid2_t;

/*!
 * @name Constants and macros for entire MTBDWT_PERIPHID2 register
 */
/*@{*/
#define HW_MTBDWT_PERIPHID2_ADDR(x) ((x) + 0xFE8U)

#define HW_MTBDWT_PERIPHID2(x)   (*(__I hw_mtbdwt_periphid2_t *) HW_MTBDWT_PERIPHID2_ADDR(x))
#define HW_MTBDWT_PERIPHID2_RD(x) (HW_MTBDWT_PERIPHID2(x).U)
/*@}*/

/*
 * Constants & macros for individual MTBDWT_PERIPHID2 bitfields
 */

/*!
 * @name Register MTBDWT_PERIPHID2, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
/*@{*/
#define BP_MTBDWT_PERIPHID2_PERIPHID (0U)  /*!< Bit position for MTBDWT_PERIPHID2_PERIPHID. */
#define BM_MTBDWT_PERIPHID2_PERIPHID (0xFFFFFFFFU) /*!< Bit mask for MTBDWT_PERIPHID2_PERIPHID. */
#define BS_MTBDWT_PERIPHID2_PERIPHID (32U) /*!< Bit field size in bits for MTBDWT_PERIPHID2_PERIPHID. */

/*! @brief Read current value of the MTBDWT_PERIPHID2_PERIPHID field. */
#define BR_MTBDWT_PERIPHID2_PERIPHID(x) (HW_MTBDWT_PERIPHID2(x).U)
/*@}*/
/*******************************************************************************
 * HW_MTBDWT_PERIPHID3 - Peripheral ID Register
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_PERIPHID3 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtbdwt_periphid3
{
    uint32_t U;
    struct _hw_mtbdwt_periphid3_bitfields
    {
        uint32_t PERIPHID : 32;        /*!< [31:0]  */
    } B;
} hw_mtbdwt_periphid3_t;

/*!
 * @name Constants and macros for entire MTBDWT_PERIPHID3 register
 */
/*@{*/
#define HW_MTBDWT_PERIPHID3_ADDR(x) ((x) + 0xFECU)

#define HW_MTBDWT_PERIPHID3(x)   (*(__I hw_mtbdwt_periphid3_t *) HW_MTBDWT_PERIPHID3_ADDR(x))
#define HW_MTBDWT_PERIPHID3_RD(x) (HW_MTBDWT_PERIPHID3(x).U)
/*@}*/

/*
 * Constants & macros for individual MTBDWT_PERIPHID3 bitfields
 */

/*!
 * @name Register MTBDWT_PERIPHID3, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
/*@{*/
#define BP_MTBDWT_PERIPHID3_PERIPHID (0U)  /*!< Bit position for MTBDWT_PERIPHID3_PERIPHID. */
#define BM_MTBDWT_PERIPHID3_PERIPHID (0xFFFFFFFFU) /*!< Bit mask for MTBDWT_PERIPHID3_PERIPHID. */
#define BS_MTBDWT_PERIPHID3_PERIPHID (32U) /*!< Bit field size in bits for MTBDWT_PERIPHID3_PERIPHID. */

/*! @brief Read current value of the MTBDWT_PERIPHID3_PERIPHID field. */
#define BR_MTBDWT_PERIPHID3_PERIPHID(x) (HW_MTBDWT_PERIPHID3(x).U)
/*@}*/

/*******************************************************************************
 * HW_MTBDWT_COMPIDn - Component ID Register
 ******************************************************************************/

/*!
 * @brief HW_MTBDWT_COMPIDn - Component ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the component IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_mtbdwt_compidn
{
    uint32_t U;
    struct _hw_mtbdwt_compidn_bitfields
    {
        uint32_t COMPID : 32;          /*!< [31:0] Component ID */
    } B;
} hw_mtbdwt_compidn_t;

/*!
 * @name Constants and macros for entire MTBDWT_COMPIDn register
 */
/*@{*/
#define HW_MTBDWT_COMPIDn_COUNT (4U)

#define HW_MTBDWT_COMPIDn_ADDR(x, n) ((x) + 0xFF0U + (0x4U * (n)))

#define HW_MTBDWT_COMPIDn(x, n)  (*(__I hw_mtbdwt_compidn_t *) HW_MTBDWT_COMPIDn_ADDR(x, n))
#define HW_MTBDWT_COMPIDn_RD(x, n) (HW_MTBDWT_COMPIDn(x, n).U)
/*@}*/

/*
 * Constants & macros for individual MTBDWT_COMPIDn bitfields
 */

/*!
 * @name Register MTBDWT_COMPIDn, field COMPID[31:0] (RO)
 *
 * Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to
 * 0x0000_0005; ID3 to 0x0000_00B1.
 */
/*@{*/
#define BP_MTBDWT_COMPIDn_COMPID (0U)      /*!< Bit position for MTBDWT_COMPIDn_COMPID. */
#define BM_MTBDWT_COMPIDn_COMPID (0xFFFFFFFFU) /*!< Bit mask for MTBDWT_COMPIDn_COMPID. */
#define BS_MTBDWT_COMPIDn_COMPID (32U)     /*!< Bit field size in bits for MTBDWT_COMPIDn_COMPID. */

/*! @brief Read current value of the MTBDWT_COMPIDn_COMPID field. */
#define BR_MTBDWT_COMPIDn_COMPID(x, n) (HW_MTBDWT_COMPIDn(x, n).U)
/*@}*/

/*******************************************************************************
 * hw_mtbdwt_t - module struct
 ******************************************************************************/
/*!
 * @brief All MTBDWT module registers.
 */
#pragma pack(1)
typedef struct _hw_mtbdwt
{
    __I hw_mtbdwt_ctrl_t CTRL;             /*!< [0x0] MTB DWT Control Register */
    uint8_t _reserved0[28];
    __IO hw_mtbdwt_comp0_t COMP0;          /*!< [0x20] MTB_DWT Comparator Register */
    __IO hw_mtbdwt_mask0_t MASK0;          /*!< [0x24] MTB_DWT Comparator Mask Register */
    __IO hw_mtbdwt_fct0_t FCT0;            /*!< [0x28] MTB_DWT Comparator Function Register 0 */
    uint8_t _reserved1[4];
    __IO hw_mtbdwt_comp1_t COMP1;          /*!< [0x30] MTB_DWT Comparator Register */
    __IO hw_mtbdwt_mask1_t MASK1;          /*!< [0x34] MTB_DWT Comparator Mask Register */
    __IO hw_mtbdwt_fct1_t FCT1;            /*!< [0x38] MTB_DWT Comparator Function Register 1 */
    uint8_t _reserved2[452];
    __IO hw_mtbdwt_tbctrl_t TBCTRL;        /*!< [0x200] MTB_DWT Trace Buffer Control Register */
    uint8_t _reserved3[3524];
    __I hw_mtbdwt_devicecfg_t DEVICECFG;   /*!< [0xFC8] Device Configuration Register */
    __I hw_mtbdwt_devicetypid_t DEVICETYPID; /*!< [0xFCC] Device Type Identifier Register */
    __I hw_mtbdwt_periphid4_t PERIPHID4;   /*!< [0xFD0] Peripheral ID Register */
    __I hw_mtbdwt_periphid5_t PERIPHID5;   /*!< [0xFD4] Peripheral ID Register */
    __I hw_mtbdwt_periphid6_t PERIPHID6;   /*!< [0xFD8] Peripheral ID Register */
    __I hw_mtbdwt_periphid7_t PERIPHID7;   /*!< [0xFDC] Peripheral ID Register */
    __I hw_mtbdwt_periphid0_t PERIPHID0;   /*!< [0xFE0] Peripheral ID Register */
    __I hw_mtbdwt_periphid1_t PERIPHID1;   /*!< [0xFE4] Peripheral ID Register */
    __I hw_mtbdwt_periphid2_t PERIPHID2;   /*!< [0xFE8] Peripheral ID Register */
    __I hw_mtbdwt_periphid3_t PERIPHID3;   /*!< [0xFEC] Peripheral ID Register */
    __I hw_mtbdwt_compidn_t COMPIDn[4];    /*!< [0xFF0] Component ID Register */
} hw_mtbdwt_t;
#pragma pack()

/*! @brief Macro to access all MTBDWT registers. */
/*! @param x MTBDWT module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 *     use the '&' operator, like <code>&HW_MTBDWT(MTBDWT_BASE)</code>. */
#define HW_MTBDWT(x)   (*(hw_mtbdwt_t *)(x))

#endif /* __HW_MTBDWT_REGISTERS_H__ */
/* v33/140401/2.1.0 */
/* EOF */
